In recent years, there have been great advancements in the speed, power, and complexity of integrated circuits, such as application specific integrated circuit (ASIC) chips, random access memory (RAM) chips, microprocessor (μP) chips, and the like. These advancements have made possible the development of system-on-a-chip (SOC) devices. An SOC device integrates into a single chip many of the components of a complex electronic system, such as a wireless receiver (i.e., cell phone, a television receiver, and the like). SOC devices greatly reduce the size, cost, and power consumption of the system.
System-on-a-chip (SOC) data processors are characterized by a very high degree of integration on a single integrated circuit (IC) chip. Many of the peripheral components now integrated onto the same IC chip as a processor core would have been implemented as separate IC chips in a previous generation of processors. Advantageously, this decreases the amount of board space required, reduces the effects of noise, allows for low-voltage operations, and, in many cases, reduces the pin count of the SOC device.
Efficient power management in electronic systems is very important. The need to conserve electrical power is especially important in battery operated computer systems such as those used in laptop and handheld computers. Power management technologies are continually being developed and improved to enable end users to efficiently operate computer systems and promote power conservation. A power management module in a computer system is capable of turning off one or more computer subsystems when those computer subsystems have not been used for a specified period of time. The power management module determines the amount of time that the computer systems are turned off and the frequency with which the computer systems are turned off. The operating parameters of the power management module may be based on the preferences of the end user, application needs, and the system hardware capabilities.
Advanced Configuration and Power Interface (ACPI) is an open industry specification that has been developed by a consortium of computer manufacturing companies. The ACPI specification establishes industry standard interfaces for operating system configurations and power management systems.
The ACPI specification defines control interfaces and power state definitions. The ACPI specification defines a number of different power states for devices, buses, and data processor units. The ACPI power states are as follows: State “S0” is a working state. In State S0 the computer is on and the CPU is running. Power conservation in State S0 is on a “per device” basis. State “S1” is a sleep state. The computer appears off and the CPU is stopped. Random access memory (RAM) is refreshed and the system is running in a low power mode.
State “S2” is also a sleep state. The computer appears off and the CPU has no power. RAM is refreshed and the system is running in a lower power mode than the S1 sleep state. State “S3” is a deeper sleep state. The computer appears off and the CPU has no power. RAM is in slow refresh. The power supply is in a reduced power mode.
State “S4” is a “hibernate” state. The computer appears off. The computer hardware is completely off. The system memory has been saved to disk. State “S5” is an “off” state. The computer is off. The operating system has been shut down. Nothing has been saved. The “off” state requires a complete reboot to return to the working state (i.e., the S0 state).
The ACPI specification also defines four (4) processor power states for the CPU. The ACPI processor power states are as follows: State “C0” is a working state. In State C0 the CPU is on and executes instructions. State “C1” is an “Autohalt” state. The CPU enters State C1 when the CPU receives a “suspend on halt” instruction. Power consumption during State C1 is typically less than one watt (1 W). In State C1 the CPU is able to service cache snoops and interrupts. When a cache snoop or interrupt is detected, the CPU must temporarily “wake up” (i.e., return to State S0) to service the cache snoop or interrupt. The CPU then returns to State C1.
The next lower processor power state is State “C2”. State C2 is a “Quick Start” state. State C2 has an exit latency of approximately one microsecond (1 μs). Power consumption during State C2 is typically less than five hundred milliwatts (500 mW). In State C2 the CPU is able to service caches snoops but not interrupts. The interrupts are blocked by a chipset module.
The next lower processor power state is State “C3”. State C3 is a “Deep Sleep” state. State C3 has an exit latency of approximately one hundred microseconds (100 μs). Power consumption during State C3 is typically less than two hundred fifty milliwatts (250 mW). In State C3 the CPU is not able to service caches snoops or interrupts. The cache snoops and interrupts are blocked by a chipset module.
In a system-on-a-chip (SOC) integrated circuit (IC) many peripheral components are fabricated within the same silicon portion of the IC chip as the central processing unit (CPU). This feature makes the process of powering down the SOC integrated circuit chip more complicated that it would otherwise be if the peripheral components were external to the SOC integrated circuit chip. Because the central processing unit (CPU) and the peripheral components are located on the same silicon portion of the integrated circuit chip a software process is not capable of cleanly shutting down the various SOC modules. It is necessary to employ hardware to coordinate the shutting down of power to the various SOC modules as they are placed in a sleep state.
Therefore, there is a need in the art for an apparatus and method that is capable of efficiently initiating a sleep state in a system-on-a-chip (SOC) device. Specifically, there is a need in the art for an apparatus and method that is capable of employing hardware to coordinate the shutting down of power to various modules of a system-on-a-chip (SOC) device while the system-on-a-chip (SOC) device is being placed into a sleep state.